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HT49R70A-1/HT49C70-1/HT49C70L LCD Type 8-Bit MCU
Technical Document
* Tools Information * FAQs * Application Note - HA0017E Controlling the Read/Write Function of the HT24 Series EEPROM Using the HT49 Series MCUs - HA0024E Using the RTC in the HT49 MCU Series - HA0025E Using the Time Base in the HT49 MCU Series - HA0026E Using the I/O Ports on the HT49 MCU Series - HA0027E Using the Timer/Event Counter in the HT49 MCU Series - HA0075E MCU Reset and Oscillator Circuits Application Note
Features
* Operating voltage: * Buzzer output * On-chip crystal, RC and 32768Hz crystal oscillator * HALT function and wake-up feature reduce power
fSYS=4MHz: 2.2V~5.5V for HT49R70A-1/HT49C70-1 fSYS=8MHz: 3.3V~5.5V for HT49R70A-1/HT49C70-1 fSYS=500kHz: 1.2V~2.2V for HT49C70L
* 8 input lines * 16 bidirectional I/O lines * Two external interrupt input * One 8-bit and one 16-bit programmable timer/event
consumption
* 16-level subroutine nesting * Bit manipulation instruction * 16-bit table read instruction * Up to 0.5ms instruction cycle with 8MHz system clock
counter with PFD (programmable frequency divider) function
* LCD driver with 412, 413 or 404 segments * 8K16 program memory * 2248 data memory RAM * Real Time Clock (RTC) * 8-bit prescaler for RTC * Watchdog Timer
for HT49R70A-1/HT49C70-1
* Up to 8ms instruction cycle with 500kHz system clock
for HT49C70L
* 63 powerful instructions * All instructions in 1 or 2 machine cycles * Low voltage reset/detector functions for
HT49R70A-1/HT49C70-1
* 64-pin LQFP and 100-pin QFP packages
General Description
The HT49R70A-1/HT49C70-1/HT49C70L are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for a wide range of LCD applications. The mask version HT49C70-1 and HT49C70L are fully pin and functionally compatible with the OTP version HT49R70A-1 device. The HT49C70L is a low voltage version, with the ability to operate at a minimum power supply of 1.2V, making it suitable for single cell battery applications. The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions, oscillator options, HALT and wake-up functions and buzzer driver in addition to a flexible and configurable LCD interface, enhance the versatility of these devices to control a wide range of LCD-based application possibilities such as measuring scales, electronic multimeters, gas meters, timers, calculators, remote controllers and many other LCD-based industrial and home appliance applications.
Rev. 2.20
1
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
Block Diagram
fS fS U X /4
In te rru p t C ir c u it P ro g ra m M e m o ry P ro g ra m C o u n te r STACK IN T C
TM R0C TM R0 PFD0 TM R1C TM R1 PFD1 RTC M
M
YS YS
RTC O ut P B 2 /T M R 0 P B 3 /T M R 1 TM R 0O V
U X
fS fT fS M U X
T im e B a s e O u t
1D
YS
In s tr u c tio n R e g is te r
YS
/4 RTC OSC OSC3 OSC4
MP
M U
X
DATA M e m o ry
W DT T im e B a s e
W DT OSC PC 0~PC7 PORT B P B 0 /IN T 0 P B 1 /IN T 1 P B 2 /T M R 0 P B 3 /T M R 1 PB4~PB7 PORT A PA PA PA PA PA E N /D IS 0 /B Z 1 /B Z 2 3 /P F D 4~PA7
In s tr u c tio n D ecoder ALU T im in g G e n e r a tio n
MUX
PC
STATUS PB
S h ifte r
BP OSC2 OSC4 OS RE VD VS OS S S D C3 L C D D r iv e r C1 ACC LCD M e m o ry PA
H ALT
L V D /L V R C O M 0~ COM2 C O M 3/ SEG 40 SEG 0~ SEG 39
Rev. 2.20
2
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
Pin Assignment
SEG1 SEG1 SEG1 SEG SEG OSC OSC VD OSC OSC RE P A 0 /B P A 1 /B PA P A 3 /P F PA D D S Z 1 8 9 2 3 4 Z
PB PB PB2 PB3
PA5 PA6 PA7 0 /IN T 0 1 /IN T 1 /T M R 0 /T M R 1 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 VSS
1 2 3 4 5 6 7 8 9
64636261605958575655545352515049
10 11 12 13 14 15
16 1718192021 2223242526272829303132
4 0 1 2
2
HT4 HT HT 64
9R 49 49 LQ
70 C7 C7 FP
A -1 0 -1 0L -A
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
SEG SEG SEG SEG SEG SEG SEG COM COM COM COM C2 C1 V2 V1 VLC D 29 30 31 32 33 34 35 3 /S E G 4 0 0 1 2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4
SEG SEG SEG SEG SEG SEG SEG SEG SEG OSC OSC VD OSC OSC RE P A 0 /B P A 1 /B PA P A 3 /P F PA D S Z 1 2 3 4 4 2 0 1 2 3 4 5 6 7 8 Z D
PB PB2 PB3
PB
PA6 PA7 0 /IN T 0 1 /IN T 1 /T M R 0 /T M R 1 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 NC NC NC NC NC VSS
7 8 9
PA N N N N N
C C C C
5
80 79 78 77
5
76 6 75 74 73 72 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 4445 46 4748 49 50 71 70 69 68
C
HT49 HT4 HT4 100
R7 9C 9C QF
0 A -1 7 0 -1 70L P -A
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SEG SEG SEG NC NC NC SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG NC NC NC NC NC NC
9
10 11
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
NC SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG COM COM COM COM C2 C1 V2 V1 VLC D 30 31 32 33 34 35 36 37 38 39 3 /S E G 4 0 0 1 2
Rev. 2.20
3
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
Pad Description
Pad Name PA0/BZ PA1/BZ PA2 PA3/PFD PA4~PA7 PB0/INT0 PB1/INT1 PB2/TMR0 PB3/TMR1 PB4~PB7 I/O Options Wake-up Pull-high or None CMOS or NMOS Description PA0~PA7 constitute an 8-bit bidirectional input/output port with Schmitt trigger input capability. Each pin on port can be configured as wake-up input by options. PA0~PA3 can be configured as CMOS output or NMOS input/output with or without pull-high resistor by options. PA4~PA7 are always pull-high NMOS input/output. Of the eight bits, PA0~PA1 can be set as I/O pins or buzzer outputs by options. PA3 can be set as an I/O pin or as a PFD output also by options. PB0~PB7 constitute an 8-bit Schmitt trigger input port. Each pin on port are with pull-high resistor. Of the eight bits, PB0 and PB1 can be set as input pins or as external interrupt control pins (INT0) and (INT1) respectively, by software application. PB2 and PB3 can be set as an input pin or as a timer/event counter input pin TMR0 and TMR1 also by software application. PC0~PC7 constitute an 8-bit bidirectional input/output port with Schmitt trigger input capability. On the port, such can be configured as CMOS output or NMOS input/output with or without pull-high resistor by options. Voltage pump for HT49R70A-1/HT49C70-1. LCD power supply for HT49C70L. LCD power supply for HT49R70A-1/HT49C70-1. Voltage pump for HT49C70L. Voltage pump SEG40 can be set as a segment or as a common output driver for LCD panel by options. COM0~COM2 are outputs for LCD panel plate. LCD driver outputs for LCD panel segments OSC1 and OSC2 are connected to an RC network or a crystal (by options) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock. The system clock may come from the RTC oscillator. If the system clock comes from RTCOSC, these two pins can be floating. Real time clock oscillators. OSC3 and OSC4 are connected to a 32768Hz crystal oscillator for timing purposes or to a system clock source (depending on the options). No built-in capacitor Positive power supply Negative power supply, ground Schmitt trigger reset input, active low
I/O
I
3/4
PC0~PC7
I/O
Pull-high or None CMOS or NMOS 3/4 3/4 3/4 1/2, 1/3 or 1/4 Duty 3/4
V2 VLCD V1, C1, C2 COM0~COM2 COM3/SEG40 SEG0~SEG39
I I I O O
OSC1 OSC2
I O
Crystal or RC
OSC3 OSC4 VDD VSS RES
I O 3/4 3/4 I
RTC or System Clock 3/4 3/4 3/4
Rev. 2.20
4
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
Absolute Maximum Ratings
HT49R70A-1/HT49C70-1 Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW HT49C70L Supply Voltage ...........................VSS-0.3V to VSS+2.5V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ................................................................50mA Total Power Dissipation .....................................150mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total..............................................................-30mA Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
HT49R70A-1 and HT49C70-1 Test Conditions Symbol Parameter VDD VDD VLCD IDD1 Operating Voltage LCD Power Supply (Note *) Operating Current (Crystal OSC) Operating Current (RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (fSYS=RTC OSC) Standby Current (*fS=T1) Standby Current (*fS=RTC OSC) Standby Current (*fS=WDT RC OSC) Standby Current (*fS=RTC OSC) Standby Current (*fS=RTC OSC) 3/4 3/4 3V 5V 3V 5V 5V 3V No load 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V No load, system HALT, LCD Off at HALT No load, system HALT, LCD On at HALT, C type No load, system HALT LCD On at HALT, C type No load, system HALT, LCD On at HALT, R type, 1/2 bias No load, system HALT, LCD On at HALT, R type, 1/3 bias No load, fSYS=8MHz No load, fSYS=4MHz Conditions LVR disable, fSYS=4MHz fSYS=8MHz VA5.5V No load, fSYS=4MHz 2.2 3.3 2.2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 1 3 1 3 4 0.3 0.6 3/4 3/4 2.5 10 2 6 17 34 13 26 5.5 5.5 5.5 2 5 2 5 8 0.6 1 1 2 5 20 5 10 30 60 25 50 V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Min. Typ. Max. Unit Ta=25C
IDD2
IDD3
IDD4
ISTB1
ISTB2
ISTB3
ISTB4
ISTB5
Rev. 2.20
5
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
Test Conditions Symbol Parameter VDD ISTB6 Standby Current (*fS=WDT RC OSC) Standby Current (*fS=WDT RC OSC) Input Low Voltage for I/O Ports, TMR and INT Input High Voltage for I/O Ports, TMR and INT Input Low Voltage (RES) Input High Voltage (RES) I/O Port Sink Current 5V IOH1 3V I/O Port Source Current 5V IOL2 LCD Common and Segment Current LCD Common and Segment Current Pull-high Resistance 5V VLVR VLVD Note: Low Voltage Reset Voltage Low Voltage Detector Voltage 3/4 3/4 3V 5V 3V 5V 3V 3/4 3/4 3/4 VOH=0.9VDD VOL=0.1VDD VOH=0.9VDD 3V 5V 3V 5V 3/4 3/4 3/4 3/4 3V Conditions No load, system HALT, LCD On at HALT, R type, 1/2 bias No load, system HALT, LCD On at HALT, R type, 1/3 bias 3/4 3/4 3/4 3/4 VOL=0.1VDD 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 6 10 -2 -5 210 350 -80 -180 20 10 2.7 3.0 14 28 10 20 3/4 3/4 3/4 3/4 12 25 -4 -8 420 700 -160 -360 60 30 3.2 3.3 25 50 20 40 0.3VDD VDD 0.4VDD VDD 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 100 50 3.6 3.6 mA mA mA mA V V V V mA mA mA mA mA mA mA mA kW kW V V Min. Typ. Max. Unit
ISTB7
VIL1 VIH1 VIL2 VIH2 IOL1
IOH2
RPH
* for the value of VA refer to the LCD driver section. *fS please refer to the WDT clock option
Rev. 2.20
6
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
HT49C70L Test Conditions Symbol VDD IDD1 IDD2 IDD4 ISTB1 ISTB2 ISTB3 VIL1 VIH1 VIL2 VIH2 IOL1 IOH1 RPH VLVR VLVD Note: Parameter VDD Operating Voltage Operating Current (Crystal OSC) Operating Current (RC OSC) Operating Current (fSYS=RTC OSC) Standby Current (*fS=T1) Standby Current (*fS=RTC OSC) Standby Current (*fS=WDT RC OSC) Input Low Voltage for I/O Ports, TMR and INT Input High Voltage for I/O Ports, TMR and INT Input Low Voltage (RES) Input High Voltage (RES) I/O Port Sink Current I/O Port Source Current Pull-high Resistance Low Voltage Reset Voltage Low Voltage Detector Voltage 3/4 3/4 Conditions 1.2 3/4 3/4 3/4 3/4 3/4 3/4 0 0.8VDD 0 0.9VDD 0.4 -0.3 75 2.7 3.0 3/4 60 50 2.5 0.1 1 0.5 3/4 3/4 3/4 3/4 0.8 -0.6 150 3.2 3.3 2.2 100 100 5 0.5 2 1 0.3VDD VDD 0.4VDD VDD 3/4 3/4 300 3.6 3.6 V mA mA mA mA mA mA V V V V mA mA kW V V Min. Typ. Max. Unit
1.5V No load, fSYS=455kHz 1.5V No load, fSYS=400kHz 1.5V No load 1.5V 1.5V 1.5V 3/4 3/4 3/4 3/4 No load, system HALT, LCD Off at HALT No load, system HALT, LCD On at HALT, C type No load, system HALT LCD On at HALT, C type 3/4 3/4 3/4 3/4
1.5V VOL=0.1VDD 1.5V VOH=0.9VDD 1.5V 3/4 3/4 3/4 3/4 3/4
* for the value of VA refer to the LCD driver section. *fS please refer to the WDT clock option
Rev. 2.20
7
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
A.C. Characteristics
HT49R70A-1 and HT49C70-1 Test Conditions Symbol Parameter VDD fSYS1 System Clock (Crystal OSC) System Clock (RC OSC) System Clock (32768Hz Crystal OSC) RTC Frequency Timer I/P Frequency 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3V 5V tRES tSST tLVR tINT Note: External Reset Low Pulse Width System Start-up Timer Period Low Voltage Width to Reset Interrupt Pulse Width *tSYS= 1/fSYS1, 1/fSYS2 or 1/fSYS3 Ta=25C Test Conditions Symbol fSYS1 fSYS2 fSYS3 fRTCOSC fTIMER Parameter VDD System Clock (Crystal OSC) System Clock (RC OSC) System Clock (32768Hz Crystal OSC) RTC Frequency Timer I/P Frequency 3/4 3/4 3/4 3/4 3/4 Conditions 1.2V~2.2V 1.2V~2.2V 3/4 3/4 1.2V~2.2V 400 400 3/4 3/4 0 35 10 3/4 0.5 10 3/4 3/4 32768 32768 3/4 70 3/4 1024 1 3/4 500 500 3/4 3/4 500 140 3/4 3/4 2 3/4 kHz kHz Hz Hz kHz ms ms *tSYS ms ms Min. Typ. Max. Unit 3/4 3/4 3/4 3/4 Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5.5V 3/4 3/4 2.2V~5.5V 3.3V~5.5V 3/4 3/4 Wake-up from HALT 3/4 3/4 400 400 400 400 3/4 3/4 0 0 45 32 1 3/4 0.5 1 3/4 3/4 3/4 3/4 32768 32768 3/4 3/4 90 65 3/4 1024 1 3/4 4000 8000 4000 8000 3/4 3/4 4000 8000 180 130 3/4 3/4 2 3/4 kHz kHz kHz kHz Hz Hz kHz kHz ms ms ms *tSYS ms ms Min. Typ. Max. Unit Ta=25C
fSYS2
fSYS3 fRTCOSC fTIMER
tWDTOSC Watchdog Oscillator Period
HT49C70L
tWDTOSC Watchdog Oscillator Period tRES tSST tLVR tINT Note: External Reset Low Pulse Width System Start-up Timer Period Low Voltage Width to Reset Interrupt Pulse Width *tSYS= 1/fSYS1, 1/fSYS2 or 1/fSYS3
1.5V 3/4 3/4 3/4 3/4 3/4 3/4 Wake-up from HALT 3/4 3/4
Rev. 2.20
8
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
Functional Description
Execution Flow The system clock is derived from either a crystal or an RC oscillator or a 32768Hz crystal oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme makes it possible for each instruction to be effectively executed in a cycle. If an instruction changes the value of the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) is 13 bits wide and it controls the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 8192 addresses. After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by 1. The PC then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; otherwise proceed to the next instruction. The lower byte of the PC (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations.
T2 T3 T4 T1 T2 T3 T4
S y s te m O S C 2 (R C
C lo c k o n ly ) PC
T1
T2
T3
T4
T1
PC
PC+1
PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter *12 0 0 0 0 0 0 0 *12 #12 *11 0 0 0 0 0 0 0 *11 #11 *10 0 0 0 0 0 0 0 *10 #10 *9 0 0 0 0 0 0 0 *9 #9 S9 *8 0 0 0 0 0 0 0 *8 #8 S8 *7 0 0 0 0 0 0 0 @7 #7 S7 *6 0 0 0 0 0 0 0 @6 #6 S6 *5 0 0 0 0 0 0 0 @5 #5 S5 *4 0 0 0 0 1 1 1 @4 #4 S4 *3 0 0 1 1 0 0 1 @3 #3 S3 *2 0 1 0 1 0 1 0 @2 #2 S2 *1 0 0 0 0 0 0 0 @1 #1 S1 *0 0 0 0 0 0 0 0 @0 #0 S0
Mode Initial Reset External Interrupt 0 External Interrupt 1 Timer/Event Counter 0 overflow Timer/Event Counter 1 overflow Time Base Interrupt RTC Interrupt Skip Loading PCL Jump, Call Branch Return From Subroutine
Program Counter + 2
S12 S11 S10
Program Counter Note: *12~*0: Program counter bits #12~#0: Instruction code bits S12~S0: Stack register bits @7~@0: PCL bits
Rev. 2.20
9
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
When a control transfer takes place, an additional dummy cycle is required. Program Memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 819216 bits which are addressed by the program counter and table pointer. Certain locations in the ROM are reserved for special usage:
* Location 000H
000H 004H 008H 00CH 010H 014H 018H D e v ic e in itia liz a tio n p r o g r a m E x te r n a l in te r r u p t 0 s u b r o u tin e E x te r n a l in te r r u p t 1 s u b r o u tin e T im e r /e v e n t c o u n te r 0 in te r r u p t s u b r o u tin e T im e r /e v e n t c o u n te r 1 in te r r u p t s u b r o u tin e T im e B a s e In te r r u p t R T C In te rru p t P ro g ra m ROM
Location 000H is reserved for program initialization. After chip reset, the program always begins execution at this location.
* Location 004H
n00H nFFH
L o o k - u p ta b le ( 2 5 6 w o r d s )
1F00H 1FFFH
L o o k - u p ta b le ( 2 5 6 w o r d s ) 1 6 b its N o te : n ra n g e s fro m 0 to 1 F
Location 004H is reserved for the external interrupt service program. If the INT0 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004H.
* Location 008H
Program Memory
* Table location
Location 008H is reserved for the external interrupt service program also. If the INT1 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 008H.
* Location 00CH
Location 00CH is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
* Location 010H
Location 010H is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 010H.
* Location 014H
Any location in the ROM can be used as a look-up table. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to TBLH (Table Higher-order byte register) (08H). Only the destination of the lower-order byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of TBLH. The TBLH is read only, and the table pointer (TBLP) is a read/write register (07H), indicating the table location. Before accessing the table, the location should be placed in TBLP. All the table related instructions require 2 cycles to complete the operation. These areas may function as a normal ROM depending upon the users requirements. Stack Register - STACK The stack register is a special part of the memory used to save the contents of the program counter. The stack is organized into 16 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. Its activated level is indexed by a stack pointer (SP) and is neither readable nor writeable. At the start of a subroutine call or an interrupt acknowledgment, the contents of the program counter is pushed Table Location
Location 014H is reserved for the Time Base interrupt service program. If a Time Base interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 014H.
* Location 018H
Location 018H is reserved for the real time clock interrupt service program. If a real time clock interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 018H. Instruction(s) TABRDC [m] TABRDL [m]
*12 P12 1
*11 P11 1
*10 P10 1
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Table Location Note: *12~*0: Table location bits @7~@0: Table pointer bits P12~P8: Current program counter bits
Rev. 2.20
10
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
onto the stack. At the end of the subroutine or interrupt routine, signaled by a return instruction (RET or RETI), the contents of the program counter is restored to its previous value from the stack. After chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented (by RET or RETI), the interrupt is serviced. This feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is full, and a CALL is subsequently executed, a stack overflow occurs and the first entry is lost (only the most recent 16 return addresses are stored). Data Memory - RAM The data memory (RAM) is designed with 2458 bits, and is divided into two functional groups, namely; special function registers and general purpose data memory, most of which are readable/writeable, although some are read only. Of the two types of functional groups, the special function registers consist of an Indirect addressing register 0 (00H), a Memory pointer register 0 (MP0;01H), an Indirect addressing register 1 (02H), a Memory pointer register 1 (MP1;03H), a Bank pointer (BP;04H), an Accumulator (ACC;05H), a Program counter lower-order byte register (PCL;06H), a Table pointer (TBLP;07H), a Table higher-order byte register (TBLH;08H), a Real time clock control register (RTCC;09H), a Status register (STATUS;0AH), an Interrupt control register 0 (INTC0;0BH), a Timer/Event Counter 0 (TMR0;0DH), a Timer/Event Counter 0 control register (TMR0C;0EH), a Timer/Event Counter 1 (TMR1H:0FH;TMR1L;10H), a Timer/Event Counter 1 control register (TMR1C;11H), I/O registers (PA;12H, PB;14H, PC;16H), and Interrupt control register 1 (INTC1;1EH). On the other hand, the general purpose data memory, addressed from 20H to FFH, is used for data and control information under instruction commands. The areas in the RAM can directly handle arithmetic, logic, increment, decrement, and rotate operations. Except some dedicated bits, Each pin in the RAM can be set and reset by SET [m].i and CLR [m].i They are also indirectly accessible through the Memory pointer register 0 (MP0;01H) or the Memory pointer register 1 (MP1;03H). Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and MP1(03H) respectively. Reading location 00H or 02H indirectly returns the result 00H. While, writing it indirectly leads to no operation.
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0C H 0D H 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1C H 1D H 1EH 1FH 20H
IN T C 1 In d ir e c t A d d r e s s in g R e g is te r 0
MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH RTCC STATUS IN T C 0 TM R0 TM R0C TM R1H TM R1L TM R1C PA PB PC
S p e c ia l P u r p o s e D a ta M e m o ry
G e n e ra l P u rp o s e D a ta M e m ro y (2 2 4 B y te s ) FFH
:U nused. R e a d a s "0 "
RAM Mapping The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the RAM by combining corresponding indirect addressing registers. MP0 can only be applied to data memory, while MP1 can be applied to data memory and LCD display memory. Accumulator - ACC The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC.
Rev. 2.20
11
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ etc.)
Interrupts The device provides two external interrupts, two internal timer/event counter interrupts, an internal time base interrupt, and an internal real time clock interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. Once an interrupt subroutine is serviced, other interrupts are all blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may take place during this interval, but only the interrupt request flag will be recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 or of INTC1 may be set in order to allow interrupt nesting. Once the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack should be prevented from becoming full. All these interrupts can support a wake-up function. As an interrupt is serviced, a control transfer occurs by pushing the contents of the program counter onto the stack followed by a branch to a subroutine at the specified location in the ROM. Only the contents of the program counter is pushed onto the stack. If the contents of the register or of the status register (STATUS) is altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts are triggered by a high to low transition of INT0 or INT1, and the related interrupt request flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0) is set as well. After the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04H or 08H occurs. The interrupt request flag (EIF0 or EIF1) and EMI bits are all cleared to disable other interrupts. Function
The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS The status register (0AH) is 8 bits wide and contains, a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PDF), and a watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except for the TO and PDF flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PDF flags. Operations related to the status register, however, may yield different results from those intended. The TO and PDF flags can only be changed by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC, and C flags reflect the status of the latest operations. On entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly.
Bit No. 0
Label C
C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by either a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register
1 2 3 4 5 6, 7
AC Z OV PDF TO 3/4
Rev. 2.20
12
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F;bit 6 of INTC0), which is normally caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a subroutine call to location 0CH occurs. The related interrupt request flag (T0F) is reset, and the EMI bit is cleared to disable further interrupts. The Timer/Event Counter 1 is operated in the same manner but its related interrupt request flag is T1F (bit 4 of INTC1) and its subroutine call location is 10H. The time base interrupt is initialized by setting the time base interrupt request flag (TBF;bit 5 of INTC1), that is caused by a regular time base signal. After the interrupt is enabled, and the stack is not full, and the TBF bit is set, a subroutine call to location 14H occurs. The related interrupt request flag (TBF) is reset and the EMI bit is cleared to disable further interrupts. The real time clock interrupt is initialized by setting the real time clock interrupt request flag (RTF; bit 6 of INTC1), that is caused by a regular real time clock signal. After the interrupt is enabled, and the stack is not full, and the RTF bit is set, a subroutine call to location 18H occurs. The related interrupt request flag (RTF) is reset and the EMI bit is cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are all held until the RETI instruction is executed or the EMI bit and the related inBit No. 0 1 2 3 4 5 6 7 Label EMI EEI0 EEI1 ET0I EIF0 EIF1 T0F 3/4 terrupt control bit are set both to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI sets the EMI bit and enables an interrupt service, but RET does not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses are serviced on the latter of the two T2 pulses if the corresponding interrupts are enabled. In the case of simultaneous requests, the priorities in the following table apply. These can be masked by resetting the EMI bit. Interrupt Source External interrupt 0 External interrupt 1 Timer/Event Counter 0 overflow Timer/Event Counter 1 overflow Time base interrupt Real time clock interrupt Priority 1 2 3 4 5 6 Vector 04H 08H 0CH 10H 14H 18H
The Timer/Event Counter 0 interrupt request flag, T0F, external interrupt 1 request flag (EIF1), external interrupt 0 request flag (EIF0), enable Timer/Event Counter 0 interrupt bit (ET0I), enable external interrupt 1 bit (EEI1), enable external interrupt 0 bit (EEI0), and enable master interrupt bit (EMI) make up of the Interrupt Control register 0 (INTC0) which is located at 0BH in the RAM. The real time clock interrupt request flag (RTF), time base interrupt request flag (TBF), Timer/Event Counter 1 interrupt request flag (T1F), enable real time Function
Controls the master (global) interrupt (1=enabled; 0=disabled) Controls the external interrupt 0 (1=enabled; 0=disabled) Controls the external interrupt 1 (1=enabled; 0=disabled) Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled) External interrupt 0 request flag (1=active; 0=inactive) External interrupt 1 request flag (1=active; 0=inactive) Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) Unused bit, read as 0 INTC0 (0BH) Register
Bit No. 0 1 2 3 4 5 6 7
Label ET1I ETBI ERTI 3/4 T1F TBF RTF 3/4
Function Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled) Controls the time base interrupt (1=enabled; 0:disabled) Controls the real time clock interrupt (1=enabled; 0:disabled) Unused bit, read as 0 Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) Time base request flag (1=active; 0=inactive) Real time clock request flag (1=active; 0=inactive) Unused bit, read as 0 INTC1 (1EH) Register
Rev. 2.20
13
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
clock interrupt bit (ERTI), and enable time base interrupt bit (ETBI), enable Timer/Event Counter 1 interrupt bit (ET1I) on the other hand, constitute the Interrupt Control register 1 (INTC1) which is located at 1EH in the RAM. EMI, EEI0, EEI1, ET0I, ET1I, ETBI, and ERTI are all used to control the enable/disable status of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (RTF, TBF, T0F, T1F, EIF1, EIF0) are all set, they remain in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a software instruction. It is recommended that a program should not use the CALL subroutine within the interrupt subroutine. Its because interrupts often occur in an unpredictable manner or require to be serviced immediately in some applications. During that period, if only one stack is left, and enabling the interrupt is not well controlled, operation of the call in the interrupt subroutine may damage the original control sequence. Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. Three types of system clocks can be selected while various clock source options for the Watchdog Timer are provided for maximum flexibility. All oscillator options are selected through the configuration options. The three methods of generating the system clock are:
* External crystal/resonator oscillator * External RC oscillator * External RTC Oscillator
tion with the crystal or resonator manufacturers specification. The external parallel feedback resistor, Rp, is normally not required but in some cases may be needed to assist with oscillation start up. Internal Ca, Cb, Rf Typical Values @ 5V, 25C Ca 11~13pF Cb 13~15pF Rf 270kW
Oscillator Internal Component Values HT49R70A-1/HT49C70-1 Crystal Oscillator C1 and C2 Values Crystal Frequency 8MHz 4MHz 1MHz Note: C1 TBD TBD TBD C2 TBD TBD TBD CL TBD TBD TBD
1. C1 and C2 values are for guidance only. 2. CL is the crystal manufacturer specified load capacitor value.
Crystal Recommended Capacitor Values HT49R70A-1/HT49C70-1 Resonator C1 and C2 Values Resonator Frequency 3.58MHz 1MHz 455kHz Note: C1 TBD TBD TBD C2 TBD TBD TBD
One of these two methods must be selected using the configuration options. More information regarding the oscillator is located in Application Note HA0075E on the Holtek website.
* External Crystal/Resonator Oscillator
C1 and C2 values are for guidance only.
Resonator Recommended Capacitor Values HT49R70A-1/HT49C70-1 Resonator C1 and C2 Values Resonator Frequency 455kHz Note: C1 TBD C2 TBD
The simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, and will normally not require external capacitors. However, for some crystals and most resonator types, to ensure oscillation and accurate frequency generation, it may be necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultaC1 Rp OSC1 Rf Ca In te r n a l O s c illa to r C ir c u it
C1 and C2 values are for guidance only.
Resonator Recommended Capacitor Values HT49C70L
Cb C2 OSC2
T o in te r n a l c ir c u its
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d . 2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F .
Crystal/Resonator Oscillator
Rev. 2.20
14
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
* External RC Oscillator
Using the external system RC oscillator requires that a resistor, with a value between 24kW and 1MW for HT49R70A-1/HT47C70-1 and from 560kW and 1MW for HT49C70L, is connected between OSC1 and ground, and a capacitor is connected to VDD. The generated system clock divided by 4 will be provided on OSC2 as an output which can be used for external synchronization purposes. Note that as the OSC2 output is an NMOS open-drain type, a pull high resistor should be connected if it to be used to monitor the internal frequency. Although this is a cost effective oscillator configuration, the oscillation frequency can vary with VDD, temperature and process variations and is therefore not suitable for applications where timing is critical or where accurate oscillator frequencies are required.For the value of the external resistor ROSC refer to the Holtek website for typical RC Oscillator vs. Temperature and VDD characteristics graphics. Note that it is the only microcontroller internal circuitry together with the external resistor, that determine the frequency of the oscillator. The external capacitor shown on the diagram does not influence the frequency of oscillation.
V 470pF OSC1 R
OSC DD
selected in consultation with the crystal or resonator manufacturers specification. The external parallel feedback resistor, Rp, is normally not required but in some cases may be needed to assist with oscillation start up. Using the slower 32768Hz oscillator as the system oscillator will of course use less power. Internal Ca, Cb, Rf Typical Values @ 5V, 25C Ca TBD Cb TBD Rf TBD
RTC Oscillator Internal Component Values RTC Oscillator C1 and C2 Values Crystal Frequency 32768Hz Note: C1 TBD C2 TBD CL TBD
1. C1 and C2 values are for guidance only. 2. CL is the crystal manufacturer specified load capacitor value.
32768 Hz Crystal Recommended Capacitor Values When the system enters the Power Down Mode, the 32768Hz oscillator will keep running and if it is selected as the Timer and Watchdog Timer source clock, will also keep these functions operational. During power up there is a time delay associated with the RTC oscillator, waiting for it to start up. The QOSC bit in the RTCC register, is provided to give a quick start-up function and can be used to minimise this delay. During a power up condition, this bit will be cleared to 0 which will initiate the RTC oscillator quick start-up function. However, as there is additional power consumption associated with this quick start-up function, to reduce power consumption after start up takes place, it is recommended that the application program should set the QOSC bit high about 2 seconds after power on. It should be noted that, no matter what condition the QOSC bit is set to, the RTC oscillator will always function normally, only there is more power consumption associated with the quick start-up function.
* Watchdog Timer Oscillator
fS
YS
/4 N M O S O p e n D r a in
OSC2
RC Oscillator
* External RTC Oscillator
When the microcontroller enters the Power Down Mode, the system clock is switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep some internal functions such as timers operational even when the microcontroller is in the Power Down Mode. To do this, a 32768Hz oscillator, also known as the Real Time Clock or RTC oscillator, is provided. To implement this clock, the OSC3 and OSC4 pins should be connected to a 32768Hz crystal. However, for some crystals, to ensure oscillation and accurate frequency generation, it may be necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be
C1 32768H z Rp OSC3 Rf Ca
The WDT oscillator is a fully self-contained free running on-chip RC oscillator with a typical period of 65ms at 5V requiring no external components. When the device enters the Power Down Mode, the system clock will stop running but the WDT oscillator continues to free-run and to keep the watchdog active. However, to preserve power in certain applications the WDT oscillator can be disabled via a configuration option.
Cb C2 OSC4
T o in te r n a l c ir c u its
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d . 2 . A lth o u g h n o t s h o w n O S C 3 /O S C 4 p in s h a v e a p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F .
External RTC Oscillator
Rev. 2.20
15
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or an instruction clock (system clock/4) or a real time clock oscillator (RTC oscillator). The timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The WDT can be disabled by options. But if the WDT is disabled, all executions related to the WDT lead to no operation. The WDT time-out period is fS/2 ~fS/2 . If the WDT clock source chooses the internal WDT oscillator, the time-out period may vary with temperature, VDD, and process variations. On the other hand, if the clock source selects the instruction clock and the HALT instruction is executed, WDT may stop counting and lose its protecting purpose, and the logic can only be restarted by an external logic. When the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT can stop the system clock. The WDT overflow under normal operation initializes a chip reset and sets the status bit TO. In the HALT mode, the overflow initializes a warm reset, and only the program counter and SP are reset to zero. To clear the contents of the WDT, there are three methods to be adopted, i.e., external reset (a low level to RES), software instruction, and a HALT instruction. There are two types of software instructions; CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one type of instruction can be active at a time depending on the options - CLR
15 16
WDT times selection option. If the CLR WDT is selected (i.e., CLR WDT times equal one), any execution of the CLR WDT instruction clears the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the chip due to time-out. Multi-function Timer These devices provide a multi-function timer for the WDT , time base and RTC but with different time-out periods. The multi-function timer consists of an 8-stage divider and a 7-bit prescaler, with the clock source coming from the WDT OSC or RTC OSC or the instruction clock (i.e., system clock divided by 4). The multi-function timer also provides a selectable frequency signal (ranges from fS/22 to fS/28) for LCD driver circuits, and a selectable frequency signal (ranging from fS/22 to fS/29) for the buzzer output by options. It is recommended to select a nearly 4kHz signal for the LCD driver circuits to have proper display. Time Base The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period ranges from fS/212 to fS/215 selected by options. If time base time-out occurs, the related interrupt request flag (TBF; bit 5 of INTC1) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 14H occurs. The time base time-out signal can also be applied as a clock source of the Timer/Event Counter 1 so as to get a longer time-out period.
S y s te m
C lo c k /4 O p tio n S e le c t fS D iv id e r D iv id e r CK R W D T C le a r T CK R T
RTC O SC 32768H z W DT 12kH z OSC
T im e - o u t R e s e t fS /2
15
~ fS /2
16
Watchdog Timer
fs
D iv id e r
P r e s c a le r
O p tio n
O p tio n
L C D D r iv e r ( fS /2 2 ~ fS /2 8 ) B u z z e r (fS /2 2~ fS /2 9)
T im e B a s e In te r r u p t fS /2 12~ fS /2 15
Time Base
Rev. 2.20
16
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
Real Time Clock - RTC The real time clock (RTC) is operated in the same manner as the time base that is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to fS/215 by software programming . Writing data to RT2, RT1 and RT0 (bit 2, 1, 0 of RTCC;09H) yields various time-out periods. If the RTC time-out occurs, the related interrupt request flag (RTF; bit 6 of INTC1) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 18H occurs. The real time clock time-out signal also can be applied as a clock source of the Timer/Event Counter 0 in order to get a longer time-out period. RT2 0 0 0 0 1 1 1 1 RT1 0 0 1 1 0 0 1 1 RT0 0 1 0 1 0 1 0 1 RTC Clock Divided Factor 2 8* 2 9* 210* 211* 212 213 214 215 The system quits the HALT mode by an external reset, an interrupt, an external falling edge signal on port A, or a WDT overflow. An external reset causes device initialization, and the WDT overflow performs a warm reset. After examining the TO and PDF flags, the reason for chip reset can be determined. The PDF flag is cleared by system power-up or by executing the CLR WDT instruction, and is set by executing the HALT instruction. On the other hand, the TO flag is set if WDT time-out occurs, and causes a wake-up that only resets the PC (Program Counter) and SP, and leaves the others at their original state. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each pin in port A can be independently selected to wake up the device by options. Awakening from an I/O port stimulus, the program resumes execution of the next instruction. On the other hand, awakening from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program resumes execution at the next instruction. But if the interrupt is enabled, and the stack is not full, the regular interrupt response takes place. When an interrupt request flag is set before entering the HALT status, the system cannot be awakened using that interrupt. If wake-up events occur, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period is inserted after the wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. However, if the Wake-up results in the next instruction execution, the execution will be performed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status.
Note: * not recommended to be used Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following.
* The system oscillator turns off but the WDT or RTC
oscillator keeps running (if the WDT oscillator or the real time clock is selected).
* The contents of the on-chip RAM and of the registers
remain unchanged.
* The WDT is cleared and start recounting (if the WDT
clock source is from the WDT oscillator or the real time clock oscillator).
* All I/O ports maintain their original status. * The PDF flag is set but the TO flag is cleared. * LCD driver is still running (if the WDT OSC or RTC
OSC is selected).
fS
D iv id e r RT2 RT1 RT0
P r e s c a le r
8 to 1 M ux.
fS /2 8~ fS /2 15 R T C In te rru p t
Real Time Clock
Rev. 2.20
17
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
Reset There are three ways in which reset may occur.
* RES is reset during normal operation * RES is reset during HALT * WDT time-out is reset during normal operation
VDD RES S S T T im e - o u t C h ip R eset tS
ST
The WDT time-out during HALT differs from other chip reset conditions, for it can perform a warm reset that resets only the program counter and SP and leaves the other circuits at their original state. Some registers remain unaffected during any other reset conditions. Most registers are reset to the initial condition once the reset conditions are met. Examining the PDF and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES Wake-up HALT WDT time-out during normal operation WDT Wake-up HALT
Reset Timing Chart
HALT W DT W DT T im e - o u t R eset E x te rn a l C o ld R eset W a rm R eset
RES SST 1 0 - b it R ip p le C o u n te r P o w e r - o n D e te c tio n
OSC1
Reset Configuration
The functional unit chip reset status is shown below. Program Counter Interrupt Prescaler, Divider
V
DD
000H Disabled Cleared Cleared. After master reset, WDT starts counting Off Input mode Points to the top of the stack
Note: u stands for unchanged
V
DD
0 .0 1 m F 100kW RES 0 .1 m F B a s ic Reset C ir c u it 10kW 0 .1 m F 100kW RES H i-n o is e Reset C ir c u it
WDT, RTC, Time Base Timer/event Counter Input/output Ports Stack Pointer Timer/Event Counter
Reset Circuit Note: Most applications can use the Basic Reset Circuit as shown, however for applications with extensive noise, it is recommended to use the Hi-noise Reset Circuit. To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system awakes from a HALT state. Awaking from a HALT state, an SST delay is added. An extra option load time delay is added during reset and power on.
Two timer/event counters are implemented in the device. One of them contains an 8-bit programmable count-up counter, the other contains a 16-bit programmable count-up counter. The Timer/Event Counter 0 clock source may come from the system clock or system clock/4 or RTC time-out signal or external source. System clock source or system clock/4 is selected by options. The Timer/Event Counter 1 clock source may come from TMR0 overflow or system clock or time base time-out signal or system clock/4 or external source, and the three former clock source is selected by options. Using external clock input allows the user to count exter-
Rev. 2.20
18
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
The register states are summarized below: Register TMR0 TMR0C TMR1H TMR1L TMR1C Program Counter MP0 MP1 BP ACC TBLP TBLH STATUS INTC0 INTC1 RTCC PA PB PC Note: Reset (Power On) xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 0000 1--0000H xxxx xxxx xxxx xxxx ---- ---0 xxxx xxxx xxxx xxxx xxxx xxxx --00 xxxx -000 0000 -000 -000 --00 0111 1111 1111 xxxx xxxx 1111 1111 * stands for warm reset u stands for unchanged x stands for unknown WDT Time-out RES Reset (Norma Operation) (Normal Operation) xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 0000 1--0000H uuuu uuuu uuuu uuuu ---- ---0 uuuu uuuu uuuu uuuu uuuu uuuu --1u uuuu -000 0000 -000 -000 --00 0111 1111 1111 xxxx xxxx 1111 1111 xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 0000 1--0000H uuuu uuuu uuuu uuuu ---- ---0 uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu -000 0000 -000 -000 --00 0111 1111 1111 xxxx xxxx 1111 1111 RES Reset (HALT) xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 0000 1--0000H uuuu uuuu uuuu uuuu ---- ---0 uuuu uuuu uuuu uuuu uuuu uuuu --01 uuuu -000 0000 -000 -000 --00 0111 1111 1111 xxxx xxxx 1111 1111 WDT Time-out (HALT)* uuuu uuuu uuuu u--uuuu uuuu uuuu uuuu uuuu u--0000H uuuu uuuu uuuu uuuu ---- ---u uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu -uuu -uuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Rev. 2.20
19
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
nal events, measure time internals or pulse widths, or generate an accurate time base. While using the internal clock allows the user to generate an accurate time base. There are two registers related to the Timer/Event Counter 0; TMR0 ([0DH]), TMR0C ([0EH]). Two physical registers are mapped to TMR0 location; writing TMR0 puts the starting value in the Timer/Event Counter 0 register and reading TMR0 takes the contents of the Timer/Event Counter 0. The TMR0C is a timer/event counter control register, which defines some options. There are three registers related to the Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing TMR1L will only put the written data to an internal lower-order byte buffer (8-bit) and writing TMR1H will transfer the specified data and the contents of the lower-order byte buffer to TMR1H and TMR1L registers, respectively. The Timer/Event Counter 1 preload register is changed by each writing TRM1H operations. Reading TMR1H will latch the contents of TMR1H and TMR1L counters to the destination and the lower-order
S y s te m S y s te m C lo c k C lo c k /4 RTC O ut T0S TM R0 T0E T0M 1 T0M 0 T0O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l T im e r /E v e n t C c o u n te r 0 PFD0 O v e r flo w to In te rru p t M U X D a ta B u s T0M 1 T0M 0 T im e r /E v e n t C o u n te r 0 P r e lo a d R e g is te r R e lo a d
byte buffer, respectively. Reading the TMR1L will read the contents of the lower-order byte buffer. The TMR1C is the Timer/Event Counter 1 control register, which defines the operating mode, counting enable or disable and an active edge. The T0M0 and T0M1 (T1M0 and T1M1) bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an external (TMR0, TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR0, TMR1), and the counting is based on the internal selected clock source. In the event count or timer mode, the timer/event counter starts counting at the current contents in the timer/event counter and ends at FFH (FFFFH). Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (T0F: bit 6 of INTC0; T1F: bit 4 of INTC1).
O p tio n
f IN
T
Timer/Event Counter 0
T M R 0 O v e r flo w S y s te m C lo c k O p tio n S e le c t M U X T1S TM R1 T1E T1M 1 T1M 0 T1O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l T1M 1 T1M 0 1 6 - B it P r e lo a d R e g is te r R e lo a d L o w B y te B u ffe r D a ta B u s
T im e B a s e O u t S y s te m C lo c k /4
H ig h B y te
Low
B y te PFD1
O v e r flo w
to In te rru p t
1 6 - B it T im e r /E v e n t C o u n te r
Timer/Event Counter 1
PFD0 M U X PFD1
1 /2
PFD
P A 3 D a ta C T R L PFD S o u r c e O p tio n
PFD Source Option
Rev. 2.20
20
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
In the pulse width measurement mode with the values of the T0ON/T1ON and T0E/T1E bits equal to 1, after the TMR0 (TMR1) has received a transient from low to high (or high to low if the T0E/T1E bit is 0), it will start counting until the TMR0 (TMR1) returns to the original level and resets the T0ON/T1ON. The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only 1-cycle measurement can be made until the T0ON/T1ON is set. The cycle measurement will re-function as long as it receives further transient pulse. In this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. Bit No. 0~2 Label 3/4 Unused bit, read as 0 Defines the TMR0 active edge of the timer/event counter: In Event Counter Mode (T0M1,T0M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T0M1,T0M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable/disable timer counting (0=disabled; 1=enabled) 2 to 1 multiplexer control inputs which selects the timer/event counter clock source (0=RTC outputs; 1= system clock or system clock/4) Defines the operating mode (T0M1, T0M0) 01= Event count mode (External clock) 10= Timer mode (Internal clock) 11= Pulse Width measurement mode (External clock) 00= Unused TMR0C (0EH) Register Bit No. 0~2 Label 3/4 Unused bit, read as 0 Defines the TMR1 active edge of the timer/event counter: In Event Counter Mode (T1M1,T1M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T1M1,T1M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable/disable timer counting (0= disabled; 1= enabled) 2 to 1 multiplexer control inputs to select the timer/event counter clock source (0= option clock source; 1= system clock/4) Defines the operating mode (T1M1, T1M0) 01= Event count mode (External clock) 10= Timer mode (Internal clock) 11= Pulse Width measurement mode (External clock) 00= Unused TMR1C (11H) Register Rev. 2.20 21 December 16, 2009 Function To enable the counting operation, the Timer ON bit (T0ON: bit 4 of TMR0C; T1ON: bit 4 of TMR1C) should be set to 1. In the pulse width measurement mode, the T0ON/T1ON is automatically cleared after the measurement cycle is completed. But in the other two modes, the T0ON/T1ON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is one of the wake-up sources and can also be applied to a PFD (Programmable Frequency Divider) output at PA3 by options. Only one PFD (PFD0 or PFD1) can be applied to PA3 by options. If PA3 is set as PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0, Timer/Event Counter 1 respectively. No matter what the operation mode is, writing a 0 to ET0I or ET1I disables Function
3
T0E
4 5
T0ON T0S
6 7
T0M0 T0M1
3
T1E
4 5
T1ON T1S
6 7
T1M0 T1M1
HT49R70A-1/HT49C70-1/HT49C70L
the related interrupt service. When the PFD function is selected, executing CLR [PA].3 instruction to enable PFD output and executing SET [PA].3 instruction to disable PFD output. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs. When the timer/event counter (reading TMR0/TMR1) is read, the clock is blocked to avoid errors, as this may results in a counting error. Blocking of the clock should be taken into account by the programmer. It is strongly recommended to load a desired value into the TMR0/TMR1 register first, before turning on the related timer/event counter, for proper operation since the initial value of TMR0/TMR1 is unknown. Due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredictable result. After this procedure, the timer/event function can be operated normally. An example is given, using one 8-bit and one 16-bit width Timer (timer 0; timer 1) cascaded into 24-bit width. START: mov mov a, 09h ; Set ET0I & EMI bits to intc0, a ; enable timer 0 and ; global interrupt Input/Output Ports There are two 8-bit bidirectional input/output ports, PA and PC and one 8-bit input port PB. PA, PB and PC are mapped to [12H], [14H] and [16H] of the RAM, respectively. PA0~PA3 can be configured as CMOS (output) or NMOS (input/output) with or without pull-high resistor by options. PA4~PA7 are always pull-high and NMOS (input/output). If NMOS (input) is chosen, Each pin on the port (PA0~PA7) can be configured as a wake-up input. PB can only be used for input operation. PC can be configured as CMOS output or NMOS input/output with or without pull-high resistor by options. All the ports for the input operation (PA, PB and PC), are non-latched, that is, the inputs should be ready at the T2 rising edge of the instruction MOV A, [m] (m=12H, 14H or 16H). For PA, PC output operation, all data are latched and remain unchanged until the output latch is rewritten. When the PA and PC structures are open drain NMOS type, it should be noted that, before reading data from the pads, a 1 should be written to the related bits to disable the NMOS device. That is, executing first the instruction SET [m].i (i=0~7 for PA) to disable related NMOS device, and then MOV A, [m] to get stable data. After chip reset, these input lines remain at the high level or are left floating (by options). Each pin of these output latches can be set or cleared by the MOV [m], A (m=12H or 16H) instruction. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or to the accumulator. When a PA or PC line is used as an I/O line, the related PA or PC line options should be configured as NMOS with or without pull-high resistor. Once a PA or PC line is selected as a CMOS output, the I/O function cannot be used. The input state of a PA or PC line is read from the related PA or PC pad. When the PA or PC is configured as NMOS with or without pull-high resistor, one should be careful when applying a read-modify-write instruction to PA or PC. Since the read-modify-write will read the entire port state (pads state) first, execute the specified instruction and then write the result to the port data register. When the read operation is executed, a fault pad state (caused by the load effect or floating state) may be read. Errors will then occur. There are three function pins that share with the PA port: PA0/BZ, PA1/BZ and PA3/PFD.
mov a, 01h ; Set ET1I bit to enable mov intc1, a ; timer 1 interrupt mov a, 80h ; Set operating mode as mov tmr1c, a ; timer mode and select mask ; option clock source mov a, 0a0h ; Set operating mode as timer mov tmr0c, a ; mode and select system ; clock/4 set clr mov mov mov mov mov tmr1c.4 ; Enable then disable timer 1 tmr1c.4 ; for the first time a, 00h tmr0, a a, 00h tmr1l, a tmr1h, a ; Load a desired value into ; the TMR0/TMR1 register ; ; ; ; Normal operating ;
set tmr0c.4 set tmr1c.4 END
Rev. 2.20
22
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
V V
DD DD
W eak P u ll- u p O p tio n (P A 0 ~ P A 3 , P C ) V PA0~PA7 PC 0~PC 7
D a ta B u s W r ite C h ip R e s e t
D CK S Q
Q
C /N O (P P
MOS p tio n A0~PA3, C)
DD
W eak P u ll- u p
D a ta b u s R e a d I/O
PB0~PB7
Rea Sy W ak (P A
d I/O s te m e -u p o n ly )
O p tio n
PA, PC Input/Output Ports
PB input Port
The BZ and BZ are buzzer driving output pair and the PFD is a programmable frequency divider output. If the user wants to use the BZ/BZ or PFD function, the related PA port should be set as a CMOS output. The buzzer output signals are controlled by PA0 and PA1 data registers as defined in the following table. PA1 Data Register 0 1 X PA0 Data Register 0 0 1 PA0/PA1 Pad State PA0=BZ, PA1=BZ PA0=BZ, PA1=0 PA0=0, PA1=0
LCD Display Memory The device provides an area of embedded data memory for LCD display. This area is located from 40H to 68H of the RAM at Bank 1. Bank pointer (BP; located at 04H of the RAM) is the switch between the RAM and the LCD display memory. When the BP is set as 01H, any data written into 40H~68H will affect the LCD display. When the BP is cleared to 00H, any data written into 40H~68H is meant to access the general purpose data memory. The LCD display memory can be read and written to only by indirect addressing mode using MP1. When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display on or off, a 1 or a 0 is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and LCD pattern for the device.
COM 0 0 1 2 2 3 3 1 40H 41H 42H 43H 66H 67H 68H B it
Note: X stands for unused The PFD output signal function is controlled by the PA3 data register and the timer/event counter state. The PFD output signal frequency is also dependent on the timer/event counter overflow period. The definitions of PFD control signal and PFD output frequency are listed in the following table. Timer PA3 Data PA3 Pad PFD Timer Preload Register State Frequency Value OFF OFF ON ON Note: X X N N 0 1 0 1 U 0 PFD 0 X X fINT/ [2(256-N)] X
SEGMENT
0
1
2
3
38
39
40
Display Memory
X stands for unused U stands for unknown 256 is for TMR0. If TMR1 is used to generate PFD, the number should be 65536.
Rev. 2.20
23
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
LCD Driver Output The output number of the LCD driver device can be 412, 413 or 404 by option (i.e., 1/2 duty, 1/3 duty or 1/4 duty). The bias type LCD driver can be R type or C type for HT49R70A-1/HT49C70-1 while the bias type LCD driver can only be C type for HT49C70L. If the R bias type is selected, no external capacitor is required. If the C bias type is selected, a capacitor mounted between C1 and C2 pins is needed. The LCD driver bias voltage for HT49R70A-1/HT49C70-1 can be 1/2 bias or 1/3 bias by option, while the LCD driver bias voltage for HT49C70L can only be 1/2 bias. If 1/2 bias is selected, a capacitor mounted between V2 pin and ground is required. If 1/3 bias is selected, two capacitors are needed for V1 and V2 pins.
D u r in g a r e s e t p u ls e C O M 0 ,C O M 1 ,C O M 2 A ll L C D d r iv e r o u tp u ts N o r m a l o p e r a tio n m o d e VA VB VSS VA VB VSS
LCD bias power supply selection for HT49R70A-1/ HT49C70-1: There are two types of selections: 1/2 bias or 1/3 bias. LCD bias type selection for HT49R70A-1/HT49C70-1: This option is to determine what kind of bias is selected, R type or C type. Low Voltage Reset/Detector Functions There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in the microcontroller. These two functions can be enabled/disabled by options. Once the options of LVD is enabled, the user can use the RTCC.3 to enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5; otherwise, the LVD function is disabled.
*
COM0 COM1 CO M 2* L C D s e g m e n ts O N C O M 0 ,1 ,2 s id e s a r e u n lig h te d O n ly L C D s e g m e n ts O N C O M 0 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 1 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 2 s id e a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 , 2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 1 ,2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 ,2 s id e s a r e lig h te d HALT M ode C O M 0 ,C O M 1 ,C O M 2 * A ll L C D d r iv e r o u tp u ts
*
*
VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS S S S S S S S S S S S
VA
VA VB VSS VA VB VSS
N o te :
" * " O m it th e C O M 2 s ig n a l, if th e 1 /2 d u ty L C D is u s e d . V A = V L C D , V B = 1 /2 V L C D fo r H T 4 9 R 7 0 A -1 /H T 4 9 C 7 0 -1 V A = 2 V 2 , V B = V 2 , C ty p e fo r H T 4 9 C 7 0 L LCD Driver Output (1/3 Duty, 1/2 Bias, R/C Type)
Rev. 2.20
24
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
VA VB VC VSS VA VB VC COM1 VSS VA VB VC COM2 VSS VA VB COM3 VC VSS VA VB L C D s e g m e n ts O N C O M 2 s id e lig h te d VC VSS ty p e : " V A " 3 /2 V L C D , " V B " V L C D , " V C " 1 /2 V L C D ty p e : "V A " V L C D , "V B " 2 /3 V L C D , "V C " 1 /3 V L C D
COM0
N o te : 1 /4 d u ty , 1 /3 b ia s , C 1 /4 d u ty , 1 /3 b ia s , R
1 /3 b ia s o n ly fo r H T 4 9 R 7 0 A - 1 /H T 4 9 C 7 0 - 1
LCD Driver Output
The LVR has the same effect or function with the external RES signal which performs chip reset. During HALT state, LVR is disabled. The RTCC register definitions are listed in the table on the next page. Bit No. 0~2 3 4 5 6, 7 Label RT0~RT2 LVDC* QOSC LVDO* 3/4 Read/Write Reset R/W R/W R/W R 3/4 111B 0 0 0 3/4 Function 8 to 1 multiplexer control inputs to select the real clock prescaler output LVD enable/disable (1/0) 32768Hz OSC quick start-up oscillation 0/1: quickly/slowly start LVD detection output (1/0) 1: low voltage detected Unused bit, read as 0
Note: * For HT49R70A-1/HT49C70-1 RTCC (09H) Register
Rev. 2.20
25
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
Options The following shows the options in the device. All these options should be defined in order to ensure proper functioning system. Options OSC type selection. This option is to determine whether an RC or crystal or 32768Hz crystal oscillator is chosen as system clock. WDT Clock source selection. RTC and Time Base. There are three types of selections: system clock/4 or RTC OSC or WDT OSC. WDT enable/disable selection. WDT can be enabled or disabled by options. CLR WDT times selection. This option defines the method to clear the WDT by instruction. One time means that the CLR WDT can clear the WDT. Two times means that if both of the CLR WDT1 and CLR WDT2 have been executed, only then will the WDT be cleared. Time Base time-out period selection. The Time Base time-out period ranges from clock/212 to clock/215 Clock means the clock source selected by options. Buzzer output frequency selection. There are eight types of frequency signals for buzzer output: Clock/22~Clock/29. Clock means the clock source selected by options. Wake-up selection. This option defines the wake-up capability. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT by a falling edge. Pull-high selection. This option is to decide whether the pull-high resistance is visible or not on the PA0~PA3 and PC. (PB and PA4~PA7 are always pull-high) PA0~PA3 and PC0~PC7 CMOS or NMOS selection. The structure of PA0~PA3 and PC0~PC7 can be selected as CMOS or NMOS individually. When the CMOS is selected, the related pins only can be used for output operations. When the NMOS is selected, the related pins can be used for input or output operations. (PA4~PA7 are always NMOS) Clock source selection of Timer/Event Counter 0. There are two types of selections: system clock or system clock/4. Clock source selection of Timer/Event Counter 1. There are three types of selections: TMR0 overflow, system clock or Time Base overflow. I/O pins share with other function selections. PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs. PA3/PFD: PA3 can be set as I/O pins or PFD output. LCD common selection. There are three types of selections: 2 common (1/2 duty) or 3 common (1/3 duty) or 4 common (1/4 duty). If the 4 common is selected, the segment output pin SEG40 will be set as a common output. LCD bias power supply selection There are two types of selections: 1/2 bias or 1/3 bias for HT49R70A-1/HT49C70-1. LCD bias type selection This option is to determine what kind of bias is selected, R type or C type for HT49R70A-1/HT49C70-1. LCD driver clock selection. There are seven types of frequency signals for the LCD driver circuits: fS/22~fS/28. fS stands for the clock source selection by options. LCD ON/OFF at HALT selection LVR selection. LVR has enable or disable options LVD selection. LVD has enable or disable options PFD selection If PA3 is set as PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0, Timer/Event Counter 1 respectively.
Rev. 2.20
26
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
Application Circuits
For HT49R70A-1/HT49C70-1 Application Circuit
V
DD
VDD Reset C ir c u it RES 0 .1 m F VSS
CO M 0~CO M 3 SEG 0~SEG 39
LCD PANEL
100kW 0 .1 m F
VLC D C1
LCD 0 .1 m F
P o w e r S u p p ly
C2 V1 0 .1 m F V2 0 .1 m F
OSC C ir c u it S e e O s c illa to r S e c tio n
OSC1 OSC2 PA0~PA7 PB0~PB7 PC 0~PC 7 IN T 0 IN T 1 TM R0 TM R1 H T 4 9 R 7 0 A -1 /H T 4 9 C 7 0 -1
OSC C ir c u it S e e O s c illa to r S e c tio n
OSC3 OSC4
Rev. 2.20
27
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
For HT49C70L Application Circuit
V
100kW RES 0 .1 m F
DD
CO M 0~CO M 3 SEG 0~SEG 39
LCD PANEL
VLCD 0 .1 m F
IN T 0 IN T 1 TM R0 TM R1 OSC C ir c u it S e e O s c illa to r S e c tio n OSC C ir c u it S e e O s c illa to r S e c tio n OSC3 OSC4 OSC1 OSC2
C1 0 .1 m F C2 V1 0 .1 m F
V2 V PA0~PA7 PB0~PB7 PC 0~PC 7
DD
H T49C 70L
Rev. 2.20
28
December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
Instruction Set
Introduction C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
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Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m]
Description Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory
Cycles 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 1 1Note 1 1Note
Flag Affected Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Logic Operation
Increment & Decrement
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Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 2.20 Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z 32 December 16, 2009
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CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
Operation
Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation
Affected flag(s) CLR WDT1 Description
Operation
Affected flag(s) CLR WDT2 Description
Operation
Affected flag(s)
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CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Operation Affected flag(s) DAA [m] Description
Operation
Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description
Operation
Affected flag(s)
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INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s)
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OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Affected flag(s) RETI Description
Operation
Affected flag(s) RL [m] Description Operation
Affected flag(s) RLA [m] Description
Operation
Affected flag(s)
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RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
Affected flag(s) RLCA [m] Description
Operation
Affected flag(s) RR [m] Description Operation
Affected flag(s) RRA [m] Description
Operation
Affected flag(s) RRC [m] Description Operation
Affected flag(s) RRCA [m] Description
Operation
Affected flag(s)
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SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) SDZ [m] Description
Operation Affected flag(s) SDZA [m] Description
Operation
Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s)
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SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
Operation Affected flag(s) SIZA [m] Description
Operation Affected flag(s) SNZ [m].i Description
Operation Affected flag(s) SUB A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) SUB A,x Description
Operation Affected flag(s)
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SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None
Affected flag(s) SZ [m] Description
Operation Affected flag(s) SZA [m] Description
Operation Affected flag(s) SZ [m].i Description
Operation Affected flag(s) TABRDC [m] Description Operation
Affected flag(s) TABRDL [m] Description Operation
Affected flag(s)
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XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
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Package Information
64-pin LQFP (7mm7mm) Outline Dimensions
C D 48 33 G H
I 49 32 F
A B
E
64
17 K 1 16 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 8.90 6.90 8.90 6.90 3/4 0.13 1.35 3/4 0.05 0.45 0.09 0 Nom. 3/4 3/4 3/4 3/4 0.40 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max. 9.10 7.10 9.10 7.10 3/4 0.23 1.45 1.60 0.15 0.75 0.20 7
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100-pin QFP (14mm20mm) Outline Dimensions
C D 80 51 G H
I 81 50
F A B
E
100
31 K 1 30 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 18.50 13.90 24.50 19.90 3/4 3/4 2.50 3/4 3/4 1 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.65 0.30 3/4 3/4 0.10 3/4 3/4 3/4 Max. 19.20 14.10 25.20 20.10 3/4 3/4 3.10 3.40 3/4 1.40 0.20 7
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December 16, 2009
HT49R70A-1/HT49C70-1/HT49C70L
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2009 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 2.20
44
December 16, 2009

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